The present invention is generally directed to RAM (random access memory) arrays for use in an environment where noise or interference related components of its power usage can degrade the functioning of a system containing such RAM.
A typical RAM (random access memory) array and in particular a static RAM array, is made up of a plurality of memory cells, each of which is comprised of a plurality, typically four (4) or more transistors to form the memory cell plus two (2) transistors for addressing the cell (a typical total of six (6) transistors). Preferably the transistors are FETs. As data is written into each cell, data-dependent current surges occur and undesirable noise results. In an environment where low noise is required, e.g., in a communication system, such data-dependent noise may degrade the potential capability of the system, e.g., its ability to discern a data signal and thus decrease the effective signal-to-noise ratio. Typically, communication systems exhibit a considerable variation in the content of their data signals and thus this data dependency may limit their capability to receive data signals without increasing the transmitted signal level, which may not be feasible or desirable. Accordingly, it would be desirable to limit the noise dependency and thus extend the capability of such a system, e.g., a communication system, that uses such a RAM.
The present invention is directed to RAM (random access memory) arrays for use in an environment where noise or interference related components of its power usage can degrade the functioning of a system containing such RAM. In an exemplary system, e.g., a communication system such as described in copending, common-assigned, U.S. patent application No. 09/882,603 which is incorporated herein by reference, the RAM may be used as an intermediate storage device for digitally sampled data from a communication channel. The sampled data is then digitally processed to extract a data stream. In this exemplary system, size and power restrictions limit the ability to otherwise increase the signal-to-noise ratio by increasing the signal, i.e., the transmitter power or size. Accordingly, in systems of the present invention the effective signal-to-noise ratio is instead improved by ensuring that any noise or interference components related to writing data into the RAM are positioned outside of the bandwidth of the communicated data.
To accomplish this task, one first notes that the typical architecture for a RAM cell, specifically a static RAM cell, includes forming two pairs of cross-linked transistors, typically FETs, where a first pair represents a data xe2x80x9c1xe2x80x9d value and the second pair represents a data xe2x80x9c0xe2x80x9d value. In the known prior art, a data transition from xe2x80x9c1xe2x80x9d to a xe2x80x9c1xe2x80x9d or from a xe2x80x9c0xe2x80x9d to a xe2x80x9c0xe2x80x9d may result in minimal changes in supply current and thus minimal power-related noise. However, a data transition from a xe2x80x9c1xe2x80x9d to a xe2x80x9c0xe2x80x9d or from a xe2x80x9c0xe2x80x9d to a xe2x80x9c1xe2x80x9d will result in a power-related noise surge. Whether a power-related noise surge occurs in the prior art is thus related to the sequence of data being written into the RAM, i.e., there is an undesirable amount of data dependency.
However, in embodiments of the present invention, the data dependency is removed by causing a first non data-dependent downward power surge when data is removed from a memory cell, and a second non data-dependent upward power surge occurs when the new data is written into the memory cell. Essentially, the same overall (downward then upward) power surges occur for a xe2x80x9c1xe2x80x9d to xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d to xe2x80x9c0xe2x80x9d, or xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d transition, i.e., any data dependency is removed. Furthermore, the combination of the first and second transitions help cause the frequency component of the power surges to occur at elevated frequencies that can be more easily filtered out. In the particular exemplary embodiment of a communication system, the frequency components of the noise can be placed well above the frequency of the relevant portions of the communication signal.
While only groups of individual RAM cells (bits) corresponding to a selected data byte are affected during each write operation (typically a different group for each sequential write operation), a common differential data bus is preferably used to provide data to (or from) a selected group of RAM cells. Accordingly, while a selected group of RAM cells may only be a potential noise sources after many, e.g., 256 for an exemplary 256xc3x97N bit RAM, other write operations, the common data bus is a potential noise source for each write operation. Accordingly, the common data bus is operated in a manner similar to that previously described for the individual RAM cells, i.e., for each write operation, each side of the differential data bus is brought to a common voltage and then the respective sides of the data bus are brought to values representative of the desired data value.
A preferred RAM data memory configured for generating predictable noise or interference related components coherent with each write cycle, essentially independent of the data content of the RAM data memory, comprises: (1) a plurality of memory cells, each of which being comprised of two sets of cross-coupled transistors wherein each of the cells is capable of holding a data bit having a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d value; (2) a plurality of memory bytes wherein each of the bytes is comprised of a plurality of concurrently addressable memory cells; (3) an address circuit for selectively addressing one of the memory bytes and selecting the memory byte to be read or written and thus form a portion of a read or a write cycle, respectively; and (4) write sequencing logic for removing charge from the selectively addressed cross-coupled transistors comprising the selectively addressed memory cells of the selectively addressed memory byte having an initial byte value before adding charge to the selectively addressed cross-coupled transistors of the selectively addressed memory cells of the selectively addressed byte to cause the memory byte to correspond to a desired byte value; and whereby current transitions associated with the removing and the adding of charge from the memory cells of the memory bytes are essentially independent of any relationship between the initial byte value and the desired byte value.
A preferred method for controlling write cycles in a RAM memory such that predictable noise or interference related components are generated coherent with each write cycle, essentially independent of the data content of the RAM data memory, wherein the RAM memory is comprised of a plurality of memory cells, each of which being suitable for containing a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d data bit value, a plurality of the memory cells are essentially concurrently addressable to represent a memory byte, comprises the steps of: (1) selecting a plurality of the memory cells corresponding to a selected memory byte; (2) removing power from each of the selected memory cells, wherein the power reduction is essentially independent of the data content of each of the selected memory cells; and (3) enabling a portion of each of the selected memory cells such that the enabled portion then represents a desired data bit value and the combination of the selected memory cells then represents a desired data byte value, wherein the step of enabling a portion of each of the selected memory cells comprises providing power to selected portions of the selected memory cells and resulting in a power increase essentially independent of the desired data byte value; and wherein the magnitude of the power reduction and the power increase are essentially the same.
In a further aspect of the present invention, the RAM comprises at least two address circuits, each of which are capable of individually enabling a data byte to be written to portions of the RAM. In a still further aspect, at least one of the address circuits automatically increments with each write cycle such that it automatically selects a different portion of RAM for each sequential write cycle. In a significant feature of this automatically incrementing mode of operation, the address circuit is comprised of a row address circuit and a column address circuit, each of which contains multiple address bits and only one of each multiple address bits is altered at any one time.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.